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cache size and multi threading programming

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In order to avoid “cache thrashing” and to improve multi threaded code performance, is it possible to change the cache size in the gauss.cfg file?

To which kind of cache does the line in the gauss.cfg file refer to ? L1 or L2 ?

Tags: asked March 6, 2013

5 Answers

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The cache_size variable in the gauss.cfg file refers to L1 cache. However, it is used to to maximize the reuse of data in cache for any particular thread. The same optimum value would be correct for a single-threaded program or a multi-threaded program.

Also, this variable is rarely used now. In most cases GAUSS queries the system for CPU details and then uses that information to select the best parameters for the algorithm.

aptech
342
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To quote your answer, “In most cases Gauss queries the system for CPU details” does it mean that if I write my own multi – threaded code then Gauss will set the cache_size on its own for what is needed by the number of threads? or does it only for internally multi threaded functions ?

Let’s assume I have an Opteron with 64+64 K L1 cache, then by your experience, which is the best level of cache_size in gauss.cfg ?

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The short answer is set it to 64.

However, the optimal cache size setting is independent of how many threads you create in your code. The level at which the cache size setting is used is at the level of the individual thread.

Let’s say that you create 8 GAUSS level threads and that each of these threads create 4 threads internally. Each of these 32 threads will be handed some particular pieces of data and some functions to execute. Once the thread gets its orders, then it is here at this level when each individual thread is executing its orders that it will take into account the CPU cache size when choosing how it will execute its orders.

aptech
342
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Therefore, if I have understood it well, cache size in gauss.cfg refers to the “cache per core” which is the figure I was mentioning when I referred to an Opteron.

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Yes, it is cache per core. In almost all cases, a typical quad-core processor will have separate L1 cache per core.

aptech
342